File: CMSIS-Core Patch3: Update of core_cm3.h for compatibility with Cortex-M3 revision < r2p0

From Version CMSIS 2.00 to 2.10 the Vector Table Offset Register (VTOR) field definitions have been updated in accordance with the ARM Technical Reference Manual for Cortex-M3 r2p0. As a result the field definition for SCB_VTOR_TBLBASE were removed and the SCB_VTOR_TBLOFF_Msk extended. This creates incompatibilities with software developed for previous revisions of the Cortex-M3. A preprocessor check against the __CM3_REV macro has been added to satisfy both the old and the new register field definitions.

/* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201) /* core r2p1 */
  #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
  #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */

  #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
  #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
  #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
  #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif