ARM7EJ-S
The ARM7EJ-S processor is a 32-bit embedded processor developed with the ARMv5TE architecture. It supports 32-bit ARM instructions, including a number of Enhanced Digital Signal Processing (DSP) instructions, as well as 16-bit Thumb instructions for high code density while maintaining good performance. It also includes a Java Accelerator based on the Jazelle Technology to improve execution performance of Java byte code. The ARM7EJ-S processor uses the Harvard architecture (separate instruction and data interface) and a five stage pipeline implementation. It is mainly used for low power devices that requires Java acceleration but do not require complex OS.
| Core Overview | |
|---|---|
| Family | ARM7 |
| Architecture | ARMv5TEJ |
| Product Line | Embedded |
| Pipeline Stages | 5 |
| With Jazelle | |
| Instruction Sets | |
| ARM Instructions |  |
| Thumb Instructions | |
| Thumb2 Instructions |  |
| DSP Instructions | |
| SIMD Instructions | |
| Memory Interface | |
| Cache | |
| TCM | |
| MMU | |
| MPU | |
| Debug Interface | |
| ETM, Embedded ICE | |