ARM926EJ-S
The ARM926EJ-S processor is a 32-bit embedded processor developed with the ARMv5TEJ architecture. It supports 32-bit ARM instructions, including a number of Enhanced Digital Signal Processing (DSP) instructions, as well as 16-bit Thumb instructions for high code density while maintaining good performance. It also includes ARM Jazelle Technology to improve execution performance of Java byte code. The ARM926EJ-S processor uses the Harvard architecture (separate instruction and data interface), and also supports Instruction TCM and Data TCM, Instruction Cache and Data Cache, and an MMU. In addition, it can also be used with optional VFP9-S floating point coprocessor for floating point intensive applications, or optional MOVE coprocessor for video codec applications. The ARM926EJ-S processor is a very popular member of the widely adopted ARM9E processor family and can be used with complex OS like Windows CE, Linux, or Symbian OS, as well as a large range of Real Time Operating Systems (RTOS).
Microcontroller Vendors
| Core Overview | |
|---|---|
| Family | ARM9 |
| Architecture | ARMv5TEJ |
| Product Line | Application |
| Pipeline Stages | 5 |
| With Jazelle | |
| Instruction Sets | |
| ARM Instructions |  |
| Thumb Instructions | |
| Thumb2 Instructions |  |
| DSP Instructions | |
| SIMD Instructions | |
| Memory Interface | |
| Cache 4k-128k | |
| TCM 0 to 1MB | |
| MMU | |
| MPU | |
| Debug Interface | |
| ETM9, CoreSight, Embedded ICE | |