ARM1136J(F)-S
The ARM1136J(F)-S processor is the first processor supporting the ARMv6 architecture. It is very popular in high-end smart phones, set top boxes and PDA applications. It supports 32-bit ARM instructions, 16-bit Thumb instructions as well as Jazelle Java Acceleration technology. Beside features from ARMv5TE such as Enhanced Digital Signal Processing (DSP) instruction, the ARMv6 architecture includes a number of instructions for SIMD (Single Instruction, Multiple Data) to enhance performance in media and graphic processing, as well an optional floating point unit. The ARM1136 processor uses multiple bus interfaces to provide higher system bandwidth and also has a dedicated DMA interface bus and a low latency peripheral bus interface. The memory architecture in the ARM1136J(F)-S processor includes unaligned data support, dynamic endian switching, exclusive accesses and better context switching for multi-tasking environment. The ARM1136J(F)-S processor supports two levels of cache memory and a Memory management Unit (MMU), and supports complex OS like Windows CE, Linux, or Symbian OS, as well as a large range of Real Time Operating Systems (RTOS).
| Core Overview | |
|---|---|
| Family | ARM11 |
| Architecture | ARMv6K |
| Product Line | Application |
| Pipeline Stages | 8 |
| With Jazelle | |
| Instruction Sets | |
| ARM Instructions |  |
| Thumb Instructions | |
| Thumb2 Instructions |  |
| DSP Instructions | |
| SIMD Instructions | |
| Memory Interface | |
| Cache 4k-64k | |
| TCM 0 to 64K | |
| MMU | |
| MPU | |
| Debug Interface | |
| ETM11RV, CoreSight, Embedded ICE | |
| Power Modes | |
| Run, Dormant, Standby, Shutdown | |