ARM966E-S

The ARM966E-S processor is a 32-bit embedded processor developed with the ARMv5TE architecture. It supports 32-bit ARM instructions, including a number of Enhanced Digital Signal Processing (DSP) instructions, as well as 16-bit Thumb instructions for high code density while maintaining high performance. The ARM966E-S processor uses the Harvard architecture (separate instruction and data interface), and also supports Instruction TCM and Data TCM. In addition, it can also be used with optional VFP9-S floating point coprocessor for floating point intensive applications, or optional MOVE coprocessor for video codec applications. The ARM966E-S processor is also a member of the ARM9E processor family and can be used with large range of Real Time Operating Systems (RTOS).

Core Overview
Family	ARM9E
Architecture	ARMv5TE
Product Line	Embedded
Pipeline Stages	5
Instruction Set
ARM Instructions
Thumb Instructions
Thumb2 Instructions
DSP Instructions
SIMD Instructions
Memory Interface
Cache
TCM 0 to 64MB
MMU
MPU
Debug Interface
ETM9, CoreSight, Embedded ICE

Documents

• ARM966E-S Technical Reference Manual
• ARM966E-S Overview