Cortex-M3

The Cortex-M3 processor is a 32-bit processor designed specifically for microcontroller applications. It is based on ARMv7-M architecture, and supports the Thumb-2 instruction set, a mixed 16-bit and 32-bit instruction set which allows applications to be developed with excellent code density and high performance. A highly efficient 3-stage pipeline with branch speculation enables high performance with low power. In addition to a range of multiply, and multiply accumulate, instructions that accelerate Digital Signal Processing (DSP) applications, hardware divide instructions and saturation instructions are supported. It has a number of bit field manipulation instructions and bit band access support (bit addressable memory) which are very useful for control and data communication applications. The Cortex-M3 processor has an in-built interrupt controller that includes exception prioritization hardware, automatic exception vector generation and automatic register stacking and restoration during exception entry and exit sequences. It also allows multi-cycle instructions to be interrupted, resulting in a processor design that allows very low exception handling latency, ease of use and greatly simplified software porting. For instance, most applications can be coded entirely in C, even exception handlers can be written as standard C functions. The Cortex-M3 processor provides an optional Memory Protection Unit (MPU), and has a good selection of supported RTOS.

Core Overview
Family	Cortex
Architecture	ARMv7-M
Product Line	Embedded
Pipeline Stages	3
With NVIC
Instruction Set
ARM Instructions
Thumb Instructions
Thumb2 Instructions
DSP Instructions
SIMD Instructions
Memory Interface
Cache
TCM
MMU
MPU
Debug Interface
CoreSight
Power Modes
Dormant, Deep Sleep, Sleep Now, Sleep on Exit

Documents

• Cortex-M3 Technical Reference Manual
• Introduction to the Cortex-M3 Processor (429KB PDF)
• Cortex-M3 Overview